In their quest for faster and smaller transistors which form the basic component of any electronic gadget, researchers at the Mumbai-based Tata Institute of Fundamental Research (TIFR) have shown a simple method to solve a key problem: Fabricating a ?gate? that will help better regulate the flow of current in these miniature devices.
A field-effect transistor is an electronic switch that, like a water tap, regulates the flow of electrons between a source and drain using a gate electrode. Computer chips, for instance, probably comprise a billion transistors whose design has traditionally placed the source, drain and gate on a single plane of silicon. The push to shrink transistors further and make them faster has driven research into the use of three-dimensional nanowires that potentially can squeeze in more transistors on a chip compared to conventional semiconductors. But the key challenge, as the transistor gets smaller, is to build an efficient gate electrode that can turn off and turn on the flow of electric current quickly.
The nanowires in question would likely be a thousand times narrower than a hair.
The team from TIFR’s department of condensed matter physics and materials science recently demonstrated what’s being seen as a simple technique of fabricating a gate which would wrap itself around the nanowire and, hence, make the device more efficient. Their paper, by lead author Sajal Dhara, was published in the journal Applied Physics Letters in October.
?As transistors are being miniaturised, the concern is that the ability to control the flow of electrons through the channel of a transistor is reducing. Everybody is trying to make gates which are as close as possible,? says Mandar Deshmukh, a faculty member at TIFR’s department and a co-author of the paper. ?The normal fabrication does not allow that yet. So, what we had shown is a potentially new way of doing it but it’s not clear that it will actually be implemented by the industry.?
Deshmukh’s team fabricated a wrap-gate electrode by embedding nanowires in polymethyl methacrylate (PMMA), a transparent thermoplastic, and exposing it to an electron beam to define the electrode. Similarly, the e-beam lithography was used to define source and drain without any etching, the process currently in use.
?The electron beam at 20 KV can expose the underlying polymer resist and this is the key reason that our process reduces several steps of fabrication,? says the research paper.
?What they have fabricated and demonstrated is an important technique in terms of realising these wraparound gates in a very simple manner. It is important in terms of making a device structure. But for it to ultimately make it to the chip-level device you need to have the ability to fabricate the wire wherever you need,? says Murali Kota, chief scientist, Semiconductor Research and Development Center, IBM India. The company’s research arm has an ongoing collaboration with TIFR on various research areas, including this project.
While Deshmukh’s team has demonstrated the technique of creating the source drain and gate electrodes on nanowires spread across on a substrate, transistor chips are typically composed of millions of transistors arranged in a specific architecture.
?For this to get into industrial use, you need to be able to create these nanowires wherever you want, after which you can use the technique which Deshmukh’s group has developed to fabricate the source-drain regions,? says Kota, adding that it is a big challenge to place millions of nanowires at exact spots on a chip. ?Many people, companies, including IBM and top universities have been talking of various methods. It could be top-down lithography in the sense that you take a silicon wafer and then use lithography combined with etching. And, there are people who talk about directed self-assembly.?
Deshmukh says the team was essentially studying the flow of electrons from a physics perspective but the response to the research paper from device engineers has surprised them. The team, which has worked on the project for the last one-and-half years, now plans to take the research further by studying potential applications.
?We are now looking more in terms of device applications now. We are trying to benchmark this and test out,? says Deshmukh. ?People have done some calculations on such geometries before so we are going to look at and test some of those models.?
Ajay Sukumaran