The Design-linked incentive (DLI) scheme, a key component of India’s ₹76,000-crore semiconductor incentive programme, needs urgent revamp to better align with the capital-intensive reality of chip design, said Ajai Chowdhry, co-founder of HCL & EPIC foundation.
“The current cap of ₹15 crore per company is not feasible,” he said. “A basic chip for consumer electronics can cost upwards of ₹50 crore to design.”
What does it offer?
At present, the DLI scheme offers up to ₹15 crore in reimbursements—covering 50% of eligible design costs for integrated circuits (ICs), chipsets, systems-on-chip (SoC), and semiconductor IPs. An additional deployment-linked incentive of 4–6% on net sales is also available, capped at ₹30 crore. However, experts suggest that these limits don’t reflect the real costs of chip development.
As reported earlier by FE, the government is considering a proposal to raise the startup subsidy from ₹15 crore to ₹30 crore under the DLI scheme’s next phase.
Experts POV
As per industry experts, the scheme should be opened up to corporate MSMEs, not just startups with easing out of the 50% cost-sharing model.
“If the government is thinking of funding projects in the ₹100–200 crore range, MSMEs shouldn’t be asked to put in half the amount at the outset,” he said.
Analysts suggest that domestic design, development, and procurement must become central pillars of India’s semiconductor push. For this, the government must give procurement preference to India-designed products, especially those created by startups or MSMEs.
“Chips coming from China have significant security risks. Every chip potentially has a backdoor. During Operation Sindoor, a lot of defence systems, including CCTVs, were found to be Chinese-made,” Chowdhry explained. “This wasn’t just a proxy conflict with Pakistan — it was with China.”
Recently, EPIC Foundation had signed a strategic Memorandum of Understanding (MoU) with Germany’s Fraunhofer Group for microelectronics with the intent to leverage combined Indian and German research capabilities in the electronics and semiconductor sector, an area identified as a crucial juncture for chip design firms.