By Lakshmi N Kethamreddy
Evolution of chips is primarily driven by the ever-increasing demand for faster and larger amounts of computations in the smallest possible form factor, while also consuming the least amount of power and function! Thanks to VLSI (Very Large-Scale Integration), today’s chips house trillions of transistors, executing billions of instructions per second. How did we get here, and what does the future hold for chip designs?
We’ve come a long way
Semiconductor progress has focused on shrinking transistors for five decades, guided by “Moore’s Law.” Today, the demand for speed in smartphones, mobile internet, AI, and big data challenges traditional chip innovation. However, the miniaturization process has hit physical limits, causing a slowdown in transistor size reduction, and falling behind Moore’s Law.
As Moore’s Law hit scaling limits, innovations in transistor design shifted from Planar to 3D structures like FinFET, extending it from 14 nm to as small as 4 nm! GAA (gate-all-around) transistors, addressing short channel effects, emerged for sizes at 3 nm and below. This led to building the most advanced MBCFET™ (multi-bridge-channel FET) and Backside PDN, enabling chip sizes of 2 nm and below and ushering in the ‘Beyond Moore’ era.
What the ‘Beyond Moore’ era beholds
Today’s market demands versatile chips for various applications, integrating Analog, Digital, RF, and Sensors into a single chip. Yet, as chip size shrinks, maintaining analog performance becomes challenging. Dependence on Moore’s Law for process miniaturization struggles to meet market demands. To overcome these challenges, a solution beyond Moore’s Law—3DIC & Advanced Packaging Technology—is necessary.
Industry forecasts anticipate a 9.6% CAGR in advanced packaging sector between 2021 and 2027. This technology, including Hybrid Copper Bonding, addresses power-related issues and enhances Power and Signal Integrity. The next phase focuses on evolving Advanced Package Solutions through the heterogeneous integration of 2.5D and 3D IC packages, utilizing Redistribution Layer, Silicon Interposer/Bridge, and TSV stacking.
These new dimensional IC designs will enable vertical stacking and hyper-integration, thus, continuing the chip evolution beyond Moore’s law!
Next-gen applications driving chip innovation
Chip design technology evolves due to market demands, semiconductor material advancements, and manufacturing process improvements. 3D ICs particularly benefit High Performance Computing applications with demanding compute and memory-intensive operations.
In consumer electronics like mobile phones, 2.5D and 3D IC innovations offer a robust, economical proposition, enabling the integration of chiplets from different technology nodes into a single large package. Mobile subsystems (5G and beyond) commonly use analog circuitry in 14nm, RF (Radio Frequency) in 28nm, and CPU/GPU in 5nm, addressing cost sensitivity, low power consumption, and the need for faster Turn Around Time (TAT) to market.
Semiconductor applications in automotive systems, such as digital cockpit management, electronic control units, cellular connectivity, functional safety, and battery management demand unique solutions for extreme conditions with high reliability. In industrial electronics, IoT relies on specialty innovations in 28nm & 18nm with embedded flash, extending to diverse applications in healthcare, transportation, manufacturing, augmented reality, sensors, home security, smart lighting, automotive, consumer electronics, and beyond.
Entering a new computational era will drive the need for smaller circuits and diverse chip architectures. Future technologists will need to think innovatively, anticipating a time when physics will open doors to new possibilities. The ultimate goal is to make imagination a reality by creating a future with greater synergy between semiconductor technology, people and their everyday needs.
The author is vice-president and head – design platform engineering (Foundry), Samsung Semiconductor India Research (SSIR)