California-based Cadence Design Systems that specialises in electronic design and automation tools and services has said that the incentives under India’s semiconductor design linked incentive (DLI) are enough for startups and companies to come up with a proof-of-concept (PoC) for their idea in 18-24 months.“If a company can’t get there (PoC stage) in that period of time, then I think it would be prudent of the government to cut their losses and invest the capital into a more promising idea,” Jaswinder Ahuja, corporate vice president and India managing director of Cadence Design Systems tells Jatin Grover. Excerpts:
How is Cadence contributing to India’s semiconductor ecosystem?
We have been at the heart of helping the design ecosystem development in India for the last 35 years. Every company including multinationals that constitute the semiconductor ecosystem in India, uses Cadence software to do their chip design as well as electronic system design. Given the complexity of chip designing, a lot of advanced tools are required, that is where Cadence comes into play. Further, the company also provides the intellectual property (IP) that can be incorporated in the design.
With the design linked incentive (DLI) scheme getting rolled out, we have been helping most of the startups in design with our advanced tools and solutions.
Do you think the incentives under the semiconductor DLI scheme are enough?
The incentives that the government has put in place are good. I will worry about whether we need more money after we have about 50 companies. The companies accepted as part of DLI are still in lower double digits. The incentive is intended to help the companies to go from zero to a point where they can raise capital. Given the fact that the immediate tools are being provided free of cost to the startup, and the government is giving a 50% subsidy on manpower and other expenses, the onus also lies on the entrepreneur.
A startup should see how with these incentives they can get to a proof of concept in 18-24 months, and tap venture capitalists (VCs). In that period of time. If a company can’t get there in that period of time, then I think it would be prudent of the government to invest the capital into a more promising idea.
With Cadence working with Indian chip design startups, can you talk about their quality?
The quality of startups is good. They are working on communication chip design like NaVIC, open source processor architecture, etc. However, there will be a certain failure rate. But India’s semiconductor landscape will be completely changed, if out of the 100 companies that the government is willing to fund, we can get five unicorns.
How Cadence looks to increase revenue from India?
As more design activity happens in the country, as more startup companies grow and become successful, our market will grow eventually. We will look for commercial arrangements with the startups once they reach a certain point. Further, we also cannot rule out possibilities of big companies getting into electronics design.
What is the situation on the ground related to chip design talent absorption?
Over 400 engineering colleges in the country have access to Cadence tools. I don’t think the chip design industry will ever be that big as the IT industry. Based on what we have observed and the rate at which the industry has grown, it has an appetite to absorb 10,000-15,000 new design engineers every year.
And how about the talent base in chip manufacturing?
While the design talent base at least exists by virtue of the last 30 years of design activity in India, the chip manufacturing talent base doesn’t exist. So if Micron is going to start their ATMP (assembly, testing, marking, and packaging), there aren’t too many people who are trained to work in an ATMP right now. That is why companies like Lam Research, Applied Materials are investing along with the government to train people.
How are you seeing the growth in chip advanced packaging?
By 2030, 90% of the chips in the world will be 2.5D or 3D in nature. What this means is that with the chips becoming too big, the companies are breaking those large chips into chiplets to reduce the defects that happen during the manufacturing process. These chiplets are then put together in a 2.5D or 3D type chip using advanced packaging tools.
That is where India can focus on to bring in more outsourced semiconductor assembly and test (OSAT) manufacturing companies to do these advanced packaging of 3D-IC chips.
Do you think NVIDIA’s partnership with Reliance and Tata group will help Cadence?
This is a relatively recent announcement, so as this plays out we will see what the full scope of that is and if there is a rule for us to play. It is suffice to say that NVIDIA does the GPUs (graphic processing units) and GPUs are the preferred processor architecture for AI type workloads. And NVIDIA uses a lot of Cadence tools and techniques to do their design. So that collaboration already exists.
