Intel, AMD, Qualcomm, and other chipmakers are joining hands to give Moore’s Law a big shot in the arm

The new standard aims to create an open and interoperable protocol to combine multiple chiplets (silicon dies) into a single package.

Semiconductor shortage

Several CPU industry heavy hitters — AMD, Qualcomm, Intel, Arm, Samsung, and Taiwan Semiconductor Manufacturing Company — are coming together to redefine semiconductor manufacturing, potentially giving Moore’s Law a big shot in the arm amid a global chip shortage. The group has banded together for a new standard for chiplet-based processor design.

The new standard — Universal Chiplet Interconnect Express (UCIe) — aims to create an open and interoperable protocol to combine multiple chiplets (silicon dies) into a single package.

AMD, Intel, and many others already design or sell chiplet-based processors in various forms — AMD uses chiplets for most of its Ryzen CPUs and so will Intel’s forthcoming Sapphire Rapids Xeon processors. However, these chips use different interconnects to enable chiplet communication.

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The UCIe standard, if successful, will bring a single uniform standard, thus making it easier for smaller companies to use chiplet-based designs or for one company to include silicon produced by another company in its products.

Samsung Electronics’ memory business Vice President Cheolmin Park said they expected the UCIe consortium to foster a vibrant chiplet ecosystem.

However, conspicuous by their absence from the alliance were Apple and Nvidia. Apple has been slowly transitioning away from Intel processors to its own custom silicon chips, with the changeover scheduled to be completed by 2022.

Nvidia, a powerhouse in artificial intelligence and graphics, however, praised the UCIe consortium’s effort and welcomed an industry-standard method.

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The UCIe standard will only cover chiplet design’s physical and protocol layers. The standard will define how chiplets need to be connected to each other as well as the protocol to facilitate communication between chiplets.

However, chip designers will be given a free hand to package the chiplets in the way they see fit. This will allow the chiplets to communicate with each other directly through the package substrate or via some kind of silicon-based intermediary or bridge.

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First published on: 04-03-2022 at 17:53 IST