India will look to develop another 100,000 semiconductor engineers as part of its ₹1.27-lakh-crore Semicon 2.0 programme, as the government broadens its chip strategy from attracting fabrication plants to building capabilities across the semiconductor value chain.
The government on Monday notified detailed guidelines for Semicon 2.0, offering incentives for chip design, equipment and materials, fabrication plants, advanced packaging, research and development and talent creation.
Electronics and IT Minister Ashwini Vaishnaw said India had already achieved its earlier target of developing 85,000 semiconductor engineers in four years, against the 10 years originally envisaged. It has now set a target of adding another one lakh engineers as the global semiconductor industry faces a growing shortage of skilled workers.
“In the coming years, close to 10% of the global semiconductor industry’s market is expected to be in India. Students from Tier-II and Tier-III cities have already designed more than 250 chips,” Vaishnaw said.
The government has expanded its semiconductor design programme to 355 universities, including institutions in Tier-II and Tier-III cities. It has also identified six categories — compute, memory, radio frequency, power, networking and sensors — with around 100 chips being prioritised for development.
The expanded focus marks a shift in India’s semiconductor policy. While the first phase was centred substantially on persuading global and domestic companies to set up manufacturing and packaging facilities, Semicon 2.0 seeks to deepen the ecosystem around those investments by supporting locally designed chips, semiconductor equipment and materials, advanced packaging, R&D and skilled manpower.
The ₹1.27-lakh-crore programme is structured around six pillars — design; equipment and materials; fabrication; ATMP/OSAT; R&D; and talent development.
For large silicon wafer fabrication plants, the Centre will provide fiscal support of 40% of eligible capital expenditure, compared with 50% under the earlier programme. Projects will require a minimum investment of ₹20,000 crore.
Vaishnaw said the reduction reflected greater support from state governments as well as the progress made under the first phase, which has helped establish that semiconductor fabrication projects can be built in India.
Smaller fabs in areas such as compound semiconductors, silicon photonics and sensors, with a minimum investment of ₹500 crore, will be eligible for support of 35%. Display fabs manufacturing OLED, Micro LED or LCD panels will also be eligible for incentives of up to 35%, subject to prescribed capacity thresholds.
Packaging incentives have similarly been differentiated according to technology. Advanced packaging facilities using technologies such as 2.5D/3D packaging, wafer-level chip-scale packaging and heterogeneous integration will receive support of up to 35% of eligible capital expenditure. Conventional ATMP/OSAT plants will get 25%.
A significant addition under Semicon 2.0 is support for semiconductor equipment and materials, an area where India currently has limited domestic capabilities. The scheme covers R&D facilities for semiconductor equipment, manufacturing of semiconductor-grade raw materials, testing and characterisation facilities, and equipment manufacturing and assembly.
These segments will be eligible for 30% capital expenditure support. Equipment and component manufacturers can also receive production-linked incentives of 2-10% based on the value of components sourced domestically for five years beginning FY29, subject to an overall cap.
Chip design is another major focus. For strategic-sector chips, development will be undertaken through a competitive request-for-proposal process run by C-DAC, with intellectual property jointly owned by C-DAC and the applicant company. C-DAC, however, will not be able to commercially exploit the shared IP unless the company fails to meet its contractual obligations.
For commercially oriented chip design, startups and MSMEs can receive milestone-linked seed funding of up to ₹15 crore or 50% of project cost, whichever is lower, besides access to electronic design automation tools and multi-project wafer fabrication services.
Larger companies will have the option of royalty-based financing or equity co-investment. A deployment-linked incentive will also reimburse 9% of net sales from newly launched chips for five years, subject to prescribed caps.
R&D and talent-development projects can receive support of up to 75% of project costs, underlining the government’s attempt to create domestic capabilities beyond manufacturing.
MeitY Secretary S Krishnan said India’s semiconductor market, currently estimated at about $52 billion, is expected to reach $110-120 billion by 2030. The global market, meanwhile, could expand to $1.3-1.6 trillion by then and approach $2 trillion by 2035.
The government expects Semicon 2.0 to catalyse investments of around ₹4 lakh crore, production worth ₹2 lakh crore and exports of about ₹1 lakh crore.
India has so far approved 12 semiconductor manufacturing projects across six states under its semiconductor push. Nine are ATMP/OSAT projects. Three projects have begun commercial production this year, while two more are expected to start production by the end of 2026.