Sequence - Design for Power Seminar returns to Bangalore on Sept 10

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Sequence Design, the EDA leader in Design for Power (DFP) solutions, hosts its third annual low-power System-on-Chip (SoC) design Seminar in Bangalore on Wednesday, Sept. 10 beginning at 9am. Notable speakers from business and academia will highlight the day’s events - followed by a luncheon.

The seminar will be held at the Hotel Leela Palace, Bangalore. Interested parties may register by sending an e-mail to Sequence India’s Subrata Mukherjee at subratam@sequencedesign.com.

The keynote speaker is Mr. Manmohan Mittal, Vice President of Engineering for InSilica, a leader in custom ASIC design and image processors. Mr. Mittal will address today’s low-power challenges and solutions for major manufacturers.

Sequence customers Mr. Jithendra Srinivas, from Texas Instruments, and Mr. Shashidhara Bapat, from LSI Corporation will provide real-world examples of design success using advanced low-power EDA tools from Sequence. Also on hand will be Dr. Bharadwaj Amrutur, Assistant Professor, Indian Institute of Science, Bangalore, who will offer insights on the progress of R&D and technology trends in the low-power chip design realm.

For an overview of new products and technologies from Sequence, Mr. William Ruby, Vice President of Products & Application Engineering; and Mr. Rahul Prasad, the company’s Senior Manager, Worldwide Application Engineering & Customer Support, will describe advanced technologies for RTL low-power optimization such as the new PowerArtist™. Launched earlier this year at the Design Automation Conference, PowerArtist -,built upon Sequence’s industry-leading power-analysis technologies, -significantly increases productivity by offering the flexibility to either pinpoint and manually edit RTL, or reduce power automatically with multiple techniques for clock, datapath and memory sections of complex SoCs.